A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having a plurality of semiconductor elements such as micro transistors and resistors or a plurality of transistors operating at different voltages, a semiconductor device having transistors with improved breakdown voltages, and their manufacture methods.
B) Description of the Related Art
As the integration degree of semiconductor integrated circuit devices (IC) is improved, transistors as IC constituent elements are made very fine. The performance of logic semiconductor elements has improved considerably and many functions are fabricated on the same chip. For example, high density static random access memories (SRAM) and ultra high speed input/output circuits are mounted on the same chip as that of logic circuits.
For example, SRAM constitutes one memory cell by six transistors: two n-channel driver transistors, two p-channel load transistors, and two n-channel transfer transistors. As compared to a dynamic RAM (DRAM) constituting one memory cell by one transistor and one capacitor, although the number of constituent elements is large, the refresh operation is unnecessary. A shallow trench isolation (STI) is widely used as the isolation region of a circuit accommodating a number of semiconductor elements such as high density SRAMs at a high density. Since STI has no bird's beaks as in local oxidation of silicon (LOCOS), an area usage factor can be improved and a surface with good planarization can be obtained.
In order to reduce parasitic resistance of a resistor, salicide techniques are widely used which form a metal silicide layer on source/drain regions and a gate electrode in a self alignment manner.
Japanese Patent Laid-open Publication No. 2000-198523 discloses an SRAM utilizing STI and salicide techniques. First side wall spacers are formed on the side walls of a gate electrode, high concentration ion implantation is performed for the source/drain regions and gate electrode, and after second side wall spacers are formed, salicidation is conducted over the whole substrate surface. By setting a gate electrode side end portion of the silicide layers on the source/drain regions, away from the junction, leak current can be reduced. Circuit elements other than SRAM are not disclosed.
If transistors and other elements are integrated by independent processes, the manufacture processes become complicated and a yield lowers. It is desired to make a plurality of elements share the same process and simplify the manufacture processes as much as possible. Depending upon the circuit to be fabricated, the other element to be fabricated by the same process is a capacitor in one case and a resistor in another case. If the resistor is to be formed, it is desired that the resistance value is a desired value. If the resistance value is too high or low, this is not appropriate in many cases.
Japanese Patent Laid-open Publication No. 2000-31295 discloses a semiconductor integrated circuit device in which element isolation is performed by STI, and analog resistors in an analog-digital conversion circuit are integrated with MOS transistors with silicide layers. This Publication discloses both an analog resistor made of a diffusion layer in a silicon substrate and an analog resistor made of polysilicon on an isolation region.
A resistor region is formed independently from a transistor in order to set an optimum value of an analog resistor having several tens Ω/□ to several hundreds Ω/□. When side wall spacers are formed, a resist mask is formed on the resistor region to leave a salicide block layer made of the same layer as that of the side wall spacers. Connection regions on opposite sides of the resistor region is heavily doped with ions at the same time when high concentration regions of the transistor are formed. Thereafter, a salicidation process is performed for the whole substrate surface. Salicide layers are therefore formed on the source/drain regions and gate electrode of the transistor and on the connection regions on opposite sides of the resistor region.
Japanese Patent Laid-open Publication No. 2002-280459 discloses an integrated circuit device in which element isolation is performed by LOCOS, and transistors, capacitors and resistors are integrated. The gate electrode of a transistor and a lower electrode of a capacitor are formed at the same time by using a first polysilicon layer, and after a capacitor dielectric film is formed, an upper electrode of the capacitor and a resistor are formed by using a second polysilicon layer. The resistor is made to have a desired impurity concentration by separate ion implantation. In a salicidation process, salicide block layers are formed on the resistor and input/output transistors so as not to form silicide layers.
A desired value and precision of a resistor are decided by its use. A resistor for electrostatic discharge (ESD) protection is desired to be made of a diffusion resistor near a transistor to simplify its structure and process, although it does not require a high precision of the resistance value. An analog resistor for an input/output circuit is required to have a high precision. It is desired to have a resistance value of, e.g., about several tens Ω/□ to several hundreds Ω/□.
As a transistor becomes very fine, an operation voltage lowers, the gate insulating film becomes thin, and the gate length becomes short. The short channel effects appear such as punch-through current between the source/drain regions in an off-state of the transistor.
In order to prevent the short channel effects, the structure has been developed in which source/drain regions are formed by shallow extension regions on both sides of the gate electrode and high impurity concentration source/drain regions on both sides of the side wall spacers on the side walls of the gate electrode, and the extension regions are surrounded by opposite conductivity type pocket regions. The pocket region can be formed by ion implantation along a direction inclined from the substrate normal, the ion implantation having a longer implantation range than that of ion implantation for the extension regions.
In a system on-chip, there are strong needs for mixing a logical circuit operating at a low voltage with a different circuit such as a flash memory control circuit operating at a high voltage. In order to realize this, it is necessary to integrate the logical circuit of a low voltage operation and the flash memory control circuit of a high voltage operation on the same semiconductor substrate.
For example, integrated are a low voltage transistor at 1.2 V for a logical circuit and a high voltage transistor for a flash memory control circuit at 5 V during a reed operation and lower than 10 V during a write/erase operation. There are strong needs for further integrating middle voltage transistors at 2.5 V and 3.3 V for an input/output (I/O) circuit. The operation voltage of a low voltage transistor has a tendency that it lowers further in the future, and there is a possibility that 5 V, 1.8 V, 1.2 V and etc., are added to the operation voltage of I/O middle voltage transistors. However, only one operation voltage is often used for middle voltage transistors requested by particular customers.
It is necessary for a high voltage transistor to suppress hot electron effects and have a necessary breakdown voltage. For the structure suitable for the high voltage transistor, a gate insulating film is made thick, a gate length is elongated, lightly doped drain (LDD) regions are formed on both sides of the gate electrode, and high concentration source/drain regions are formed on both sides of the side wall spacers on side walls of the gate electrode.
Although the extension region is often called LDD region, in this specification, the region having the main object of forming a shallow junction is called extension region, whereas the region having the main object of improving a breakdown voltage is called LDD region. Although the LDD region is desired to have a low impurity concentration as this term explicitly indicates, the extension region is not required to have a low impurity concentration if the junction depth is shallow.
If an independent manufacture process matching the desired characteristics of each transistor is selected when a plurality kind of transistors are integrated, the number of processes increases and the manufacture processes become complicated, resulting in a lowered yield and a high manufacture cost. It is desired to manufacture a plurality kind of transistors by simplified processes.
Japanese Patent Laid-open Publication No. 2000-68388 discloses as prior art the fundamental manufacture method for a semiconductor integrated circuit device having CMOS transistors operating at 1.8 V and CMOS transistors operating at 3.3 V.
FIGS. 10A to 10D illustrate main processes of this fundamental manufacture method. A shallow trench isolation 102 is formed in a silicon substrate 101, and n-wells 103 and p-wells 104 are formed by ion implantation. After thin gate insulating films 105 and thick gate insulating films 106 are formed, a gate electrode layer is deposited and patterned to form gate electrodes 107.
As shown in FIG. 10A, by using a mask 112 opening the region of an n-channel MOS (NMOS) transistor operating at 1.8 V, n-type impurity, e.g., As+ ions, are implanted in a vertical direction at a relatively high concentration to form n-type extension regions 114. By using the same mask 112, p-type impurity, e.g., BF2+ ions, are implanted obliquely to form p-type pocket regions 116 outside the n-type extension regions 114.
As shown in FIG. 10B, by using a mask 118 opening the region of a p-channel MOS (PMOS) transistor operating at 1.8 V, p-type impurity, e.g., BF2+ ions, are implanted in a vertical direction at a relatively high concentration to form p-type extension regions 120. By using the same mask 118, n-type impurity, e.g., As+ ions, are implanted obliquely to form n-type pocket regions 122 outside the p-type extension regions 120.
As shown in FIG. 10C, by using a mask 124 opening the region of an NMOS transistor operating at 3.3 V, n-type impurity, e.g., P+ ions, are implanted at a relatively low concentration to form n-type LDD regions 126 capable of suppressing hot carriers.
As shown in FIG. 10D, by using a mask 128 opening the region of a PMOS transistor operating at 3.3 V, p-type impurity, e.g., BF2+ ions, are implanted to form p-type LDD regions 130 capable of suppressing leak current.
The transistor operating at 3.3 V has a long gate length and the short channel effects do not appear. The pocket regions are therefore unnecessary. If pocket regions are formed in a PMOS transistor, junction leak current increases instead.
Thereafter, side wall spacers of silicon oxide are formed on the side walls of the gate electrodes, and n- and p-type impurity ions are implanted into the NMOS and PMOS regions at a high concentration to form high concentration source/drain regions. In this manner, a multi voltage CMOS circuit operating at 1.8 V and 3.3 V is formed.
Japanese Patent Laid-open Publication No. 2000-164727 discloses a simplified manufacture method for CMOS transistors of a low voltage operation for an internal circuit and CMOS transistors of a high breakdown voltage (corresponding to the above-described middle voltage) for an I/O block.
FIGS. 11A to 11D illustrate main processes of this simplified manufacture method. In a p-type silicon substrate 201, n-type wells 202 are selectively formed, and an isolation region 203 is formed by LOCOS oxidation. There are formed thick gate insulating films 205 of 20 nm thick for high voltage operation and thin gate insulating films 206 of 7 nm thick for low voltage operation. A polysilicon layer is deposited to a thickness of 200 nm to 300 nm and patterned to form gate electrodes 207 for low voltage operation with a gate length of 0.2 to 0.4 μm and for high voltage operation with a gate length of 0.5 to 0.8 μm.
As shown in FIG. 11A, by using a resist mask 208 covering a PMOS region for low voltage operation and an NMOS region for high voltage operation, p-type impurity, boron ions, are implanted into the PMOS region for low voltage operation and the NMOS region for high voltage operation, along eight directions inclined by 50 to 60 degrees from the substrate normal, under the conditions of an acceleration energy of 40 keV to 60 keV and a dose of 5×1011 cm−2 to 10×1011 cm−2. Regions 209a and 209b doped with ions of p-type impurity B are therefore formed.
As shown in FIG. 11B, by using the same mask 208, n-type impurity, P+ ions, are implanted under the conditions of an acceleration energy of 10 keV to 30 keV and a dose of 2×1013 cm−2 to 5×1013 cm−2. In the NMOS region having the thin gate insulating film 206, n-type impurity P ions are implanted to form n-type extension regions 210a, and in the PMOS region having the thick gate insulating film 205, implanted P+ ions remain in the gate insulating film and do not reach the silicon substrate. This conclusion is given in the above-cited Publication.
As shown in FIG. 11C, by using a resist mask 211 covering a low voltage NMOS region and a high voltage PMOS, n-type impurity, P+ ions, are implanted into the low voltage PMOS region and the high voltage NMOS region, along eight directions inclined by 30 to 50 degrees from the substrate normal, under the conditions of an acceleration energy of 120 keV to 170 keV and a dose of 1×1011 cm−2 to 2×1011 cm−2, to form n-type regions 212a and 212b in the low voltage PMOS region and high voltage NMOS region.
By using the same mask 211, p-type impurity, B+ ions, are implanted under the conditions of an acceleration energy of 5 keV to 8 keV and a dose of 1×1013 cm−2 to 5×1013 cm−2, to form extension regions 214 in the low voltage PMOS region having the thin gage insulating film 106. Under these conditions, implanted p-type impurity, B+ ions, remain in the gate insulating film and do not reach the silicon substrate. This conclusion is given in the above-cited Publication.
As shown in FIG. 11D, after side wall spacers 215 are formed on the side walls of the gate electrodes 207, a resist mask 216 is formed covering the low voltage operation PMOS region and the high voltage operation PMOS region.
As+ ions as the n-type impurity are implanted under the conditions of an acceleration energy of 20 keV to 40 keV and a dose of 2.5×1015 cm−2, to form high impurity concentration (n+-type) source/drain regions 217a in the low voltage operation NMOS region and n+-type source/drain regions 217b in the high voltage operation NMOS region.
Similarly, by using a resist mask covering the NMOS region, p-type impurity ions are implanted into the PMOS region for form high impurity concentration source/drain regions. For example, high impurity concentration (p+ type) source/drain regions are formed by implanting BF2+ ions at an acceleration energy of 30 keV to 50 keV and a dose of 2×1015 cm−2 to 5×1015 cm−2.
The present inventors have found that the technologies described in Japanese Patent Laid-open Publication No. 2000-164727 cannot be reduced in practice as will be later described.